Textile yarn treatment machines

ABSTRACT

Apparatus for controlling a variable at each of a plurality of locations comprises stations at which are presented analogue values of the variable, scanning means for scanning the stations in sequence, an analogue digital converter which converts the output of the scanning means to an output signal representing in sequence and in digital form the analogue values of the scanning means output, comparator means comparing each digital equivalent with a desired value thereby to provide a sequence of difference signals, a recirculating memory which recirculates very much faster than the scanning speed of the scanning means, means for loading the memory in sequence with the difference signals at the scanning rate of the scanning means, a mark-space ratio generator for generating mark space ratios for the difference signals and means for presenting a mark-space ratio selected by the memory at each of the said locations.

States Patet Baxter et a1.

[451 Mar. 19, 197a TEXTILE YARN TREATMENT MACHINES [75] Inventors:Malcolm John Baxter; Terrence Graham Shillito, both of Manchester,England [73] Assignee: Fielden Electronics Limited,

Manchester. England [22] Filed: Oct. 13, 1972 [21] Appl. No: 297,326

[30] Foreign Application Priority Data Oct 16. 1971 Great Britain48242/71 [52] US. Cl. 340/213 R, 340/147 CN, 235/151.1 [51] Int. CL...G06f 13/06, G06f 15/06, G06f 15/46 [58] Field of Search 340/213 R, 213Q, 163; 235/151 [56] References Cited UNITED STATES PATENTS 3.541.51311/1970 Paterson 340/151 3.350.687 10/1967 Gabrielson et a1... 340/151 X3.519.807 7/1970 Jaques et a]. 235/151.1

Primary ExaminerDonald J. Yusko Attorney, Agent, or FirmBrowdy andNeimark [57] ABSTRACT Apparatus for controlling a variable at each of aplurality of locations comprises stations at which are presentedanalogue values of the variable, scanning means for scanning thestations in sequence, an analogue digital converter which converts theoutput of the scanning means to an output signal representing insequence and in digital form the analogue values of the scanning meansoutput, comparator means comparing each digital equivalent with adesired value thereby to provide a sequence of difference signals, arecirculating memory which recirculates very much faster than thescanning speed of the scanning means, means for loading the memory insequence with the difference signals at the scanning rate of thescanning means, a mark-space ratio generator for generating mark spaceratios for the difference signals and means for presenting a mark-spaceratio selected by the memory at each of thesaid locations.

12 Claims, 6 Drawing Figures TEMP ALARM INDECATOR CONVERTER sar POINT 1CIRCUIT I] i {'UNEARISER COMPARATOR i SH'FT MEMORY /[OSC1LLATOR EKDECODER 9 17 l 9 l 1 3 i 2,7COUNT'R ME%OT(Y[ l SCANNER DECODER I {5 g!L:

" 3 L 1x I x 1 COUNTER 37 -couNTER x 33 ADDER SCANNER 3 5 3i ozcoosa 45I ADDRESS 1 l LATCH LATCH [)ECODER n LATCH 47 [vii 47 PATENTEDMAR 19 m4SHEET 2 [IF 3 Q Q5 31 u m1: 2 Q a hmmwwmvmm TEXTILE YARN TREATMENTMACHINES This invention relates to apparatus for controlling a variableat each of a plurality of locations. In industrial machines andprocesses it is often required to control a variable at a large numberof locations. For example in a textile yarn heat treatment machine thetemperature at a large number of points in the machine has to be closelycontrolled and to this end a heater is provided at each point, theelectrical power to the heater being regulated to maintain thetemperature at the point between desired limits. One way in whichoverall control of the heaters of such a machine may be effected is topresent at each point to be controlled a number of mark space ratios andto gate the requisite ratio into the heater at the point thereby tocontrol in a given period the amount of energy fed to the heater. Thissystem has the disadvantage that at each controlled point it isnecessary to provide logic gates equal in number to the number of markspace ratios as well as a memory and decoder which determine theprogressive selection of the gates to be operated so as to supply thecorrect mark space ratio to the relevant heater. Control apparatus isthus multiplied by the number of points being controlled and thisapproach to the problem is most expensive because of the amount ofequipment involved. It is an object of the present invention to provideapparatus for controlling a variable at each of a plurality of locationswhich requires relatively little equipment and accordingly affords aneconomic solution to the problem.

The present invention consists in apparatus for controlling a variableat each of a plurality of locations, comprising stations at which are inoperation presented respective electrical analogue values of thevariable at the locations, scanning means for scanning the stations insequence thereby to provide an output signal representing said analoguevalues serially, an analogue to digital converter to which the outputsignal of the scanning means is supplied and which affords an output signal representing in sequence and in digital form the analogue values ofthe scanning means output signal, comparator means for comparing eachdigital equivalent of an analogue value with a desired value thereby toprovide a sequence of difference signals, a recirculating memory therecirculation rate of which is many times greater than the rate at whichthe scanning means scan from one to the next station, means for loadingthe memory in sequence with the difference signals from the comparatorat the or substantially the rate at which the scanning means scan fromone to the next station, a mark-space ratio generator for generatingmark space ratios for the difference signals and means for presenting amark-space ratio selected by the memory at each of the said locations.

Preferably, the comparator is adapted to present the difference signalsin respective categories of a predetermined number of categories and themark-space generator is adapted to provide a separate mark-space ratiofor each category.

It will be appreciated that in the apparatus of the invention the memoryis selecting at high speed and in series mark-space ratios required atthe different locations where control is being effected so that theseratios are supplied from the central control to the individual locationsand need for elaborate control equipment such as memories and decodersat each location is avoided.

Advantageously, the mark-space generator comprises a first decoderhaving a plurality of outputs, a repeating counter adapted, at the samespeed as the scanner, to supply to the decoder repeatedly a sequence ofnumbers there being one number in each sequence for each output of thedecoder and the numbers in the sequence calling up successively thedecoder outputs which correspond in number with categories of thecomparator, and, a plurality of logic gates corresponding in number withthe decoder outputs and each having an input connected in relation tothe decoder outputs so that a first of the decoder outputs connects withan input of each logic gate whilst successive outputs of the decoderafter the first connect successively with one fewer inputs of the logicgates, whereby during the period of a complete sequence of outputs ofthe decoder the logic level at the input to any particular one of thegates remains at one logic level for a proportion of the perioddepending on the number of decoder outputs to which it is connected andat another logic level for the balance of the period.

Suitably, the outputs of the logic gates connect with inputs of furtherlogic gate means and there is provided a memory decoder having outputscorresponding with the number of outputs of the first decoder andconnected respectively with inputs of the logic gates other than thoseconnected with the first decoder outputs, the memory decoder beingsupplied at the stepping speed of the memory successively with thedifference signals in the memory, each difference signal addressing oneonly of the memory decoder outputs according to the category of thedifference signal and the further logic gate means serving to provideoutputs of duration corresponding with the stepping of the memory eachoutput being a section of logic level corresponding with that availableat one of the logic gates at the input thereof connected to an output oroutputs of the first decoder.

In one form of the invention simultaneous switching of power from and tolarge numbers of power consuming devices is prevented and to this end atthe input to the first decoder is provided an adder unit which issupplied with the output of the repeating counter and with the output ofa second repeating counter comprising pulses at the stepping speed ofthe memory which pulses are converted in the second repeating counter toa repeated sequence of successive numbers having one number per outputof the first decoder whereby the output of the adder unit supplied tothe first decoder consists of a repeated sequence of numbers being thenumber output of the first repeating counter to which is added at memoryspeed each number of the sequence counted by the second repeatingcounter whereby each mark-space ratio of the first decoder is dividedinto a number of phases corresponding with the number of the firstdecoder outputs.

The invention will now be described, by way, of example, with referenceto the accompanying, diagrammatic drawings, in which:

FIG. 1 is a block schematic representation of apparatus, in accordancewith the invention, for controlling a variable at each of a plurality oflocations, in this instance the variable being temperature and thelocations being situated in a textile yarn heat treatment machine,

FIG. 2 illustrates in greater detail part of the apparatus of FIG. 1,

FIGS. 3a to c are truth tables showing the behaviour of components ofthe apparatus of the preceding Figures, and

FIG. 4, illustrates mark-space ratios produced by a mark space generatorforming part of the apparatus of FIGS. 1 and 2.

Referring the the drawings, in which, throughout, like parts have beenaccorded the same reference indicia, apparatus for controlling yarntemperature in a textile yarn heat treatment machine comprises a scanner3 in which a scanning element 5 traverses a number, in this instance 160stations x, to 1 dwelling at each of said stations for two cycles of themains supply, i.e., for 40 milliseconds in the case of a 50 Hz A.C.mains supply. At each of the stations x to x is available a voltagebeing an analogue equivalent value of the temperature measured by athermocouple of a particular point in the textile yarn heat treatmentmachine connected to the station.

The temperature analogue voltages at the stations of the scanner 3 areaccordingly supplied in sequence to an analogue to digital converter 7have a source of pulses in the form of an oscillator 9 the frequency ofwhich is in the neighbourhood of 1 MHz.

To reject the effects of periodic noise at the supply frequency theanalogue to digital converter, which is of known form operating on thedual-slope ramp principle, integrates the input signal thereto from thescanner over a precise cycle period of the supply and this requires theoscillator frequency to be a precise multiple of the supply frequency.This is achieved by feedback adjustment of the oscillator frequency.

During the mains cycle following an integration the integral in theconverter is returned to zero at a fixed reference rate in a timedepending on the value of the integral and during this time pulses fromthe oscillator provide the digital equivalent of the integrated input.Accordingly the output from the converter 7 is a series of digitalsignals, which conveniently are produced in the converter in knownmanner in binary form and are representative of the analogue voltages atthe stations X1 t0 X160.

Because the voltage output of a thermocouple is nonlinear with respectto the temperature being measured the binary signals from the converter7 are supplied to a lineariser 11 where in known manner a binary numberis added to or subtracted from each binary input to correct the latterso that the binary output from the lineariser increments equally perincremental change of temperature at any point in the machine.

The linearised binary output from the lineariser is fed to a comparator15 where it is compared with the binary representation of a desiredtemperature value referred to hereinafter as the set point value whichis supplied from circuit 13. In the comparator the comparison iseffected by adding the value of the lower number input to the complementof the larger input. Thus if the set point exceeds the input from thelineariser, the latter is added to the complement of the former and viceversa. If the comparator 15 is set for the wrong number, i.e., toreceive the complement of a number rather than the number itself, thecircuit becomes overloaded and thereby caused to reset itself to receivethe correct values of the two inputs thereto. The operating state of thecomparator accordingly indicates the polarity of the difierence betweenan input from the lineariser and the set point value and forms the firstdigit of a four bit word output from the comparator. The other threehits of the four bit word indicate an error naught to seven times achosen error. With the polarity bit, the four bits define sixteen errorconditions of which two i O are the same. Accordingly the comparatoroutput expresses the difference between a particular temperature and adesired value in any of fifteen categories, a zero category, sevenpositive and seven negative categories.

The comparator output is supplied to a memory 17 including a high speedcirculating shift register 19 which circulates four bit word inputs fromthe comparator, the four bit word being clocked along the shift registerby a memory clock 21 in the form of an oscillator which provides clockpulses at high frequency e.g. lOO Khz. At this clocking frequency thefour bit words are advanced in the shift register every 10 microseconds,whilst, as hereinafter described, the shift register is updated by theinsertion of four-bit words from the comparator every 40 milliseconds(in the case of a 50 cycle supply), i.e., at the rate the scannertraverses the stations x, to r Thus at the typical values given theshift register steps at 4,000 times the rate at which four bit wordsfrom the comparator 15 are fed thereto.

The clocking of four bit words into the memory from the comparator iseffected by bringing into correspondence binary words from a scanneraddress unit 23 and from a repeating counter 25 connected to the memoryclock 21. The scanner address unit 23 has supplied thereto a pulse fromthe scanner everytime the scanner moves from one to the next of stationsx to r and provides a sequence of outputs of binary representations ofnumbers 1 to 160 which outputs step along at the scanner address speed,i.e., typically every 40 milliseconds.

The output of the scanner address unit is employed via a decoder 24 todrive the scanner 3 so that the dwell of the scanner is synchronisedwith the scanner address unit output.

The repeating counter 25 counts every 160 pulses from the clock 21 andprovides a sequence of outputs also representing in binary form numbers1 to 160. This sequence repeats at 4,000 times, for the typical valuesstated, the speed of the sequence of outputs from the scanner address.

The outputs from the unit 23 and repeating counter 25, are supplied to aseries of exclusive OR gates, shown here as single exclusive OR gate 27which when the inputs thereto are in correspondence provide an enablingpulse which enters into the shift register 19 of the memory the outputat the comparator thus updating the memory with new data identifying thecategory of the error in relation to the set point of the temperature ata particular location in the machine. It may be observed here thatwhilst reference is made herein to a set point, the set point value neednot be the same for all temperature points. Also for convenience it willbe assumed that the machine is working at the typical values given,i.e., mains frequency 50 cycles per second, scanner speed 40milliseconds at each scanned point and a memory clock frequency of1M.Hz.

The output of the memory shift register is supplied to a memory decoder29 which operates, as hereinafter explained, in conjunction with ascanner decoder 31 which serves as a mark-space generator and which issupplied with the output of a repeating counter 33 by way of an adderunit 35 which is also supplied from a repeating counter 37 connected tothe memory clock 21. The decoders 29 and 31 each have sixteen outputs 015 one only of which responds to any one input by changing from logiclevel 1 to logic level 0. Decoder 31, ignoring for the present theeffect of adder unit 35, receives input signals from counter 33 inbinary form representing numbers 0 to 15 in sequence and the counter 33is supplied with a pulse from the converter 7 whenever the scanneradvances. The outputs 0 to 15 of decoder 31 are accordingly reducedsequentially from logic level 1 to logic level 0 every 40 milliseconds.During the 40 milliseconds dwell at logic level 0 at one of the outputsof decoder 31, the memory decoder 29 experiences a sequence of 4,000signals each of 10 micorseconds at either one or more of its 16 outputsand this sequence, because of the clocking into the input of the memoryduring this period of one word only from the comparator, is updated withdata which appears 1.6 milliseconds later at the memory output todecoder 29.

The outputs of the decoder 29 connect with respective inputs of OR-gatescollectively indicated at 39. For ease of description these OR-gates arehereinafter individually identified with reference to the output ofdecoder 29 to which they are connected. Thus OR-gate O is connected tooutput 0 of decoder 29 and so forth.

OR-gate is connected by respective diodes 40 with each of the sixteenoutputs of decoder 31 so that when any output of decoder 31 is broughtto logic level 0 the connected input of gate 15 is brought to logiclevel 0. One input of OR-gate 14 is likewise connected to outputs 0 to14 of decoder 31 by diodes so that its input so connected is brought tologic level 0 whenever any of the outputs 0 to 14 of decoder 31 islowered to logic level 0.

The connection between OR-gate 13 and decoder 31 is likewise such that asignal at any of outputs 0 to 13 of decoder 31 brings the inputconnected therewith of the gate 13 to logic level 0. As one progressesto OR- gate 0 the number of outputs to which connections via diodes 40are made reduces, the number of outputs to which OR-gate 0 is connectedbeing one.

The outputs of OR-gates 0 15 provide inputs of an AND-gate 41 the outputof which is connected to provide parallel inputs to \each of 160 D-typeflip-flop latches. These latches are supplied serially with 10microsecond clock pulses from a memory address decoder 45 the input ofwhich is connected to the output of the repeating counter which repeatsa count in binary form of numbers 1 to 160. Thus the number inputs tothe memory address decoder are converted to respective l0 microsecondclock pulses which are supplied in sequence repeatedly to the latches43.

As mentioned earlier the decoder 31 acts as a markspace generator andthe manner in which this is brought about will now be described. TheFIGS. 3a to 0 illustrate the behaviour of the OR-gates 0-15, theAND-gate 41 and the D-type flip-flop latches. It will be seen that inthe case of an OR-gate logic level 1 appearing at any or all of itsinputs results in logic level 1 appearing at its output. In the case ofthe AND-gate logic level 1 only appears at the output if all inputs areat that level. With the D-type latches the column Q+ shows what happensto the output Q when the next clock pulse is received. It will thereforebe appreciated that whatever maybe the logic level at the D input to thelatch that level is transferred to the output Q by the next clock pulse.

Looking now more particularly at FIGS. 2 and 4 and considering thesituation where outputs 0 to 15 of decoder 31 are signalled in sequenceby the inputs thereto from repeating counter 33 and are accordinglybrought in sequence each to logic level 0 for a period of 40milliseconds, it still being assumed that the adder unit 35 has noeffect. The total period of this sequence is 32 cycles of the supply asshown in the upper part of FIG. 4, i.e., 0.64 seconds or one tenth ofthe total scan time of scanner 3. If the voltage of the input of gate 0connected to output 0 of decoder 31 by a diode 40 is viewed for the fullperiod of the 0.64 seconds sequence it will be seen that for the first40 milliseconds the logic level is 0 and for the rest of the period itis at level 1. Accordingly if at any time during the first 40milliseconds the OR-gate 0 is addressed by a 10 microsecond signal atoutput 0 of decoder 29 the two inputs of OR- gate 0 are then at logiclevel 0 for the duration of the 10 microsecond signal so that the outputof the gate 0 is brought to level 0. The output of all other gates 1 15are however high since although their inputs which are connected tooutput 0 of decoder 31 are at level 0' their other inputs are atlevel 1. Thus the inputs to AND-gate 41 from OR-gate 0 is at level 0 andfrom OR gates 1-15 is at level 1. This means that the output of AND-gate41 is at level 0. During any subsequent 40 millisecond period of the0.64 second sequence, since the level of the OR-gate 0 input connectedto output 0 of decoder 31 is at level 1, a 10 microsecond signal at theoutput 0 of decoder 29 will leave the output of OR-gate 0 at level 1 sothat all inputs to and therefore the output from AND-gate 41 are atlevel 1. Accordingly during the 0.64 second period the logic level 1being mark or 0 being space prevailing at the input of OR-gate 0connected to output 0 of decoder 31 is reproduced at the output ofAND-gate 41. Thus at anytime in the 0.64 second sequence that gate 0 isaddressed by an ouput (i.e., a lowering of the logic level from 1 to 0)at point 0 of decoder 29, for 10 microseconds the mark or spacecondition of the input of OR-gate 0 prevailing at the input of that gateconnected to output 0 of decoder 31 is supplied to all the latches 43 inparallel and the particular latch being at that time addressed by thememory address decoder 45 is updated until the next time it is clocked,i.e., 1.6 milliseconds later. The latch 43 being addressed at that timecorresponds with the word output of the memory to decoder 29. Thus thememory output and the latch being addressed and therefore updated are atthe same point in the memory sequence.

If one now looks at the voltage of OR-gate 1 during the 0.64 secondsequence at the input to the gate connected via a diode 40 to outputpoints 0 and 1 of the decoder 31, it is seen that during the first andsecond 40 millisecond periods of the sequence the voltage level is 0 andduring the rest of the 0.64 seconds it is at level 1. If during thefirst milliseconds, therefore, OR-gate 1 is addressed by a 10microsecond signal from decoder 29 the output of AND-gate 41 is at level0 but for the rest of the 0.64 second sequence the AND-gate output is atlevel 1 whenever gate 1 is addressed. In general therefore the markspace signal at the input of any one of the OR-gates connected to thedecoder 31 via diodes 40 is reproduced for 10 microseconds at the outputof AND-gate 41, and therefore at the D-inputs of all latches 43 wheneverthat one of the OR-gates is addressed from the decoder 29. The signalfrom decoder 29 thus calls up from the decoder 31 that part of themark-space ratio required every 10 microseconds at the latches andrepeats this for any particular latch at 1.6 microsecond invervals. FIG.4 thus shows the mark space ratios at OR-gate to 15, or at the output ofgate 4! for the whole 0.64 second sequence a microsecond section of oneof which is presented to the D-inputs of latches 43 for each output ofthe decoder 29, i.e., each lowering from level 1 to level 0 of an outputof decoder 29 by a four bit word at its input.

The outputs of the latches are connected to respective n p n transistors47 which commence to conduct when the latch output is at level 1.Conduction of any of the transistors causes a DC voltage to be appliedto the gate electrode of a triac (not shown) there being one triac pertransistor 47. The firing of a particular triac turns on a heater at therelevant one of the 160 points of the textile machine and the triacremains in conduction for the balance of the prevailing half cycle ofthe mains supply.

Firing of the triacs is accordingly by the mark space ratio applied tothe latches and any particular latch will remain in its condition for 40milliseconds after which its condition may or may not change dependingon whether the updating of the memory involves change.

The energy supplied to the heaters is accordingly programmed independence upon the content of the memory which is being updated by thesame or fresh data relating to one of the 160 points in the machinewhenever during the 40 millisecond scanner dwell at that point thescanner address output and the output of counter correspond.

it is desirable in the context of embodiments of the invention wherelarge numbers of electrical power consuming devices are employed such asthe heaters of the present embodiment to avoid simultaneously startingof mark periods at all or large numbers of these devices which wouldinvolve interrupted heavy loads on the mains. It is the purpose of theadder unit to ensure that this cannot happen.

Accordingly the adder unit adds a binary number 0 to 15 to the binarynumber output from the repeating counter 33. The added number is derivedfrom repeating counter 37 which repeatedly counts number 0 to 15 at thespeed of memory clock 21, i.e., at 10 microsecond intervals. The binarynumber supplied to decoder 31 therefore except when counter 37 adds thevalue 0 is in advance of the binary number at the output of the counter33. Thus during the milliseconds that a particular binary number isavailable at the output of counter 33 it is having added to it at 10microsecond intervals a number which in successive intervals goes from 0to 15 and then repeats. Accordingly during a 40 millisecond'period theoutputs of decoder 31 are repeatedly sequenced, the stepping from one tothe next output being at 10 microsecond intervals whereas without theadder unit the dwell at each output was 40 milliseconds. It will be seentherefore that for any particular number at the output of counter 33 andwhich remains there for 40 milliseconds, instead of getting out of thedecoder 31 a 40 millisecond slice of one mark space ratio, there isobtained serially l0 microsecond slices of all the phases of a markspace ratio or looked at another way 10 microsecond slices of one markspace ratio which every 10 microseconds is phase advanced effectively by40 6.4 seconds. Accordingly in any period of 40 milliseconds the phaseadvancing effect at 40 millisecond intervals of the mark-space ratiogenerated staggers the onset of mark periods into 16 groups evenly overthe 6.4 second period so that the required load demand is more evenlydistributed over that period.

The apparatus is provided with temperature indicating and alarm devices.These devices 52 and S3 respectively are connected each to the output ofthe lineariser 11. The alarm circuit is somewhat similar to thecomparator l5 and compares the measured temperature from the lineariser11 with upper and lower alarm limits an alarm signal being obtained whenthe measured temperature goes outside the alarm limits. A connection tothe indicator 51 from the alarm 53 provides that when there is an alarmsignal the indicator is arrested to provide the temperature at theparticular point in the locations of the machine which is in the alarmcondition. The alarm circuit in known manner by use of delay circuits isarranged not to respond to spurious signals such as transients and willonly respond if the alarm is present for a predetermined number ofcycles of the scanner 3. The alarm may be a visual or audible alarm.

The indicator 51 uses a gallium arsenide diode display and incorporatesa repeating counter which can count from 0 to 160 at either a steppingspeed equal to the speed of the scanner, i.e., 40 milliseconds per stepor a stepping speed equal to the speed of each complete scan, i.e., 6.4seconds per step. On the faster speed of the indicator counter, theindicator will stop at the first point in an alarm condition. Releasingthe fast scan control and actuating it again causes the indicator toscan again at the higher speed to the next point in an alarm condition.At the slow speed thereof the indicator counter advances the indicatedposition once per complete scan of the scanner.

It will be appreciated that whilst the apparatus has been described inrelation to temperature control it could of course be used to effectcontrol of other variables at a number of spaced locations. Also thetypical figures quoted can be changed in any manner appropriate to thecontext in which the invention is being applied.

We claim:

1. Apparatus for controlling a variable at each of a plurality oflocations, comprising stations at which are presented respectiveelectrical analogue values of the variable at the locations, scanningmeans for scanning the stations in sequence thereby to provide an outputsignal representing said analogue values in series, an analogue todigital converter to which the output signal of the scanning means issupplied and which affords an output signal representing in sequence andin digital form the analogue values of the scanning means output signal,comparator means for comparing each digital equivalent of an analoguevalue with a desired value thereby to provide a sequence of differencesignals in respective categories of a predetermined number ofcategories, a recirculating memory the recirculation rate of which ismany times greater than the rate at which the scanning means scan fromone to the next station, means for loading the memory in sequence withthe difference signals from the comparator at the or substantially therate at which the scanning means scan from one to the next station, amark-space ratio generator for generating mark space ratios for therespective categories of difference signals provided by the comparatormeans and means for presenting a mark-space ratio selected by the memoryat each of said locations.

2. Apparatus as claimed in claim ll, wherein the mark-space generatorcomprises a first decoder having a plurality of outputs, a repeatingcounter adapted, at the same speed as the scanner, to supply to thedecoder repeatedly a sequence of numbers there being one number in eachsequence for each output of the decoder and the numbers in the sequencecalling up successively the decoder outputs which correspond in numberwith the categories of the comparator, and, a plurality of logic gatescorresponding in number with the decoder outputs and each having aninput connected in relation to the decoder outputs so that a first ofthe decoder outputs connects with an input of each logic gate whilstsuccessive outputs of the decoder after the first connect successivelywith one fewer inputs of the logic gates, whereby during the period of acomplete sequence of outputs of the decoder the logic level at the inputto any particular one of the gates remains at one logic level for aproportion of the period depending on the number of decoder outputs towhich it is connected and at another logic level for the balance of theperiod.

3. Apparatus as claimed in claim 2, wherein the outputs of the logicgates connect with inputs of further logic gate means and there isprovided a memory decoder having outputs corresponding with the numberof outputs of the first decoder and connected respectively with inputsof the logic gates other than those connected with the first decoderoutputs, the memory decoder being supplied at the stopping speed of thememory successively with the difference signals in the memory, eachdifference signal addressing one only of the memory decoder outputsaccording to the category of the difference signal and the further logicgate means serving to provide outputs of duration corresponding with thestepping of the memory each output being a section of the logic levelcorresponding with that available at one of the logic gates at the inputthereof connected to an output or outputs of the first decoder.

41. Apparatus as claimed in claim 3, wherein at the input to the firstdecoder is provided an adder unit which is supplied with the output of asecond repeating counter comprising the output of the repeating counterand with pulses at the stepping speed of the memory which pulses areconverted in the second repeating counter to a repeated sequence ofsuccessive numbers having one number per output of the first decoderwhereby the output of the adder unit supplied to the first decoderconsists of a repeated sequence of numbers being the number output ofthe first repeating counter to which is added at memory speed eachnumber of the sequence counted by the second repeating counter wherebyeach mark-space ratio of the first decoder is divided into a number ofphases phases corresponding with the number of the first decoderoutputs.

5. Apparatus as claimed in claim 3, wherein the output of the furtherlogic gate is supplied in parallel to latches respectively associatedwith the locations where a variable is to be controlled thereby tooperate the latches with mark-space ratios generated by the firstdecoder.

6. Apparatus as claimed in claim 5, wherein the latches are adapted eachto control the supply of power to a device at one location forcontrolling the variable at that location.

7. Apparatus as claimed in claim 5, wherein the latches are sequentiallyoperated at the speed of the memory.

8. Apparatus as claimed in claim 1, wherein the means for loading thememory comprise a repeating counter which provides a repeating count ofsuccessive numbers equal to the number of stations and at the speed ofthe scanner and a further repeating counter which provides at the speedof the memory a repeating count of successive numbers equal to thenumber of stations, the output of the repeating counter and furtherrepeating counter being supplied to logic gate means which when the twocounters correspond provide an output which operates the memory so as toadmit thereto the difference signal at the output of the comparator.

9. Apparatus as claimed in claim 1, wherein indicator means are providedand connected to the analogue to digital converter and are adapted tooperate at either of two speeds, a fast speed at which the values of theanalogue of variable at the stations is successively indicated and aslow speed at which said analogue values are successively indicatedafter each complete scan of the scanner.

10. Apparatus as claimed in claim 9, wherein there is provided an alarmunit which compares each digital value from the converter with alarmlimits and triggers an alarm when any digital value lies outside thealarm limits, the alarm unit being connected to the indicator means sothat when the latter is operating at its fast speed, it will be arrestedat the first alarm condition and when made to scan again at its fastspeed it will be arrested at the next alarm condition.

11. Apparatus as claimed in claim 10, wherein the alarm unit isconnected with the memory and thereby adapted not to be triggered untilan alarm condition has circulated in the memory a predetermined numberof times.

12. Apparatus as claimed in claim 1, wherein there the variable beingcontrolled.

1. Apparatus for controlling a variable at each of a plurality oflocations, comprising stations at which are presented respectiveelectrical analogue values of the variable at the locations, scanningmeans for scanning the stations in sequence thereby to provide an outputsignal representing said analogue values in series, an analogue todigital converter to which the output signal of the scanning means issupplied and which affords an output signal representing in sequence andin digital form the analogue values of the scanning means output signal,comparator means for comparing each digital equivalent of an analoguevalue with a desired value thereby to provide a sequence of differencesignals in respective categories of a predetermined number ofcategories, a recirculating memory the recirculation rate of which ismany times greater than the rate at which the scanning means scan fromone to the next station, means for loading the memory in sequence withthe difference signals from the comparator at the or substantially therate at which the scanning means scan from one to the next station, amark-space ratio generator for generating mark space ratios for therespective categories of difference signals provided by the comparatormeans and means for presenting a mark-space ratio selected by the memoryat each of said locations.
 2. Apparatus as claimed in claim 1, whereinthe mark-space generator comprises a first decoder having a plurality ofoutputs, a repeating counter adapted, at the same speed as the scanner,to supply to the decoder repeatedly a sequence of numbers there beingone number in each sequence for each output of the decoder and thenumbers in the sequence calling up successively the decoder outputswhich correspond in number with the categories of the comparator, and, aplurality of logic gates corresponding in number with the decoderoutputs and each having an input connected in relation to the decoderoutputs so that a first of the decoder outputs connects with an input ofeach logic gate whilst successive outputs of the decoder after the firstconnect successively with one fewer inputs of the logic gates, wherebyduring the period of a complete sequence of outputs of the decoder thelogic level at the input to any particular one of the gates remains atone logic level for a proportion of the period depending on the numberof decoder outputs to which it is connected and at another logic levelfor the balance of the period.
 3. Apparatus as claimed in claim 2,wherein the outputs of the logic gates connect with inputs of furtherlogic gate means and there is provided a memory decoder having outputscorresponding with the number of outputs of the first decoder andconnected respectively with inputs of the logic gates other than thoseconnected with the first decoder outputs, the memory decoder beingsuppliEd at the stopping speed of the memory successively with thedifference signals in the memory, each difference signal addressing oneonly of the memory decoder outputs according to the category of thedifference signal and the further logic gate means serving to provideoutputs of duration corresponding with the stepping of the memory eachoutput being a section of the logic level corresponding with thatavailable at one of the logic gates at the input thereof connected to anoutput or outputs of the first decoder.
 4. Apparatus as claimed in claim3, wherein at the input to the first decoder is provided an adder unitwhich is supplied with the output of a second repeating countercomprising the output of the repeating counter and with pulses at thestepping speed of the memory which pulses are converted in the secondrepeating counter to a repeated sequence of successive numbers havingone number per output of the first decoder whereby the output of theadder unit supplied to the first decoder consists of a repeated sequenceof numbers being the number output of the first repeating counter towhich is added at memory speed each number of the sequence counted bythe second repeating counter whereby each mark-space ratio of the firstdecoder is divided into a number of phases phases corresponding with thenumber of the first decoder outputs.
 5. Apparatus as claimed in claim 3,wherein the output of the further logic gate is supplied in parallel tolatches respectively associated with the locations where a variable isto be controlled thereby to operate the latches with mark-space ratiosgenerated by the first decoder.
 6. Apparatus as claimed in claim 5,wherein the latches are adapted each to control the supply of power to adevice at one location for controlling the variable at that location. 7.Apparatus as claimed in claim 5, wherein the latches are sequentiallyoperated at the speed of the memory.
 8. Apparatus as claimed in claim 1,wherein the means for loading the memory comprise a repeating counterwhich provides a repeating count of successive numbers equal to thenumber of stations and at the speed of the scanner and a furtherrepeating counter which provides at the speed of the memory a repeatingcount of successive numbers equal to the number of stations, the outputof the repeating counter and further repeating counter being supplied tologic gate means which when the two counters correspond provide anoutput which operates the memory so as to admit thereto the differencesignal at the output of the comparator.
 9. Apparatus as claimed in claim1, wherein indicator means are provided and connected to the analogue todigital converter and are adapted to operate at either of two speeds, afast speed at which the values of the analogue of variable at thestations is successively indicated and a slow speed at which saidanalogue values are successively indicated after each complete scan ofthe scanner.
 10. Apparatus as claimed in claim 9, wherein there isprovided an alarm unit which compares each digital value from theconverter with alarm limits and triggers an alarm when any digital valuelies outside the alarm limits, the alarm unit being connected to theindicator means so that when the latter is operating at its fast speed,it will be arrested at the first alarm condition and when made to scanagain at its fast speed it will be arrested at the next alarm condition.11. Apparatus as claimed in claim 10, wherein the alarm unit isconnected with the memory and thereby adapted not to be triggered untilan alarm condition has circulated in the memory a predetermined numberof times.
 12. Apparatus as claimed in claim 1, wherein there is provideda lineariser for linearising the digital outputs of the analogue todigital converter with respect to the variable being controlled.